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rev. 1.1 4/16 copyright ? 2016 by silicon laboratories si3402b-evb si3402b-evb n on -i solated e valuation b oard for the si3402b 1. description the si3402b non-isolated evaluation board (si3402b-evb rev 2) is a refer ence design for a power supply in a power over ethernet (poe) powered device (pd) applicat ion. the si3402b is described more completely in the data sheet and application notes. this document de scribes the evaluation boa rd. an evaluation board demonstrating the isolated a pplication is described in th e si3402b-iso-evb user?s guide. 2. si3402b bo ard interface ethernet data and power are applied to the board thro ugh the rj45 connector (j1). the board itself has no ethernet data transmission functionality, but, as a conveni ence, the ethernet transformer secondary is brought out to the test points. power may be applied in the following ways: ? connecting a dc source to pins 1, 2 and 3, 6 of the ethernet cable (either polarity) ? connecting a dc source to pins 4, 5 and 7, 8 of the ethernet cable (either polarity) ? using an ieee 802.3-2 015-compliant, po e-capable pse, such as trendnet tpe-1020ws the si3402b-evb board sc hematics and layout are shown in figures 1 th rough 6. the dc outpu t is at connectors j11(+) and j12(?). boards are generally shipped configured to produce +5 v output voltage but can be configured for +3.3 v or other output voltages by changing resistors r5 and r6. re fer to ?an956: using the si3402b poe pd controller in isolated and non-isolated designs? for more informat ion. the preconfigured class 3 signature can also be modified according to table 3 in an95 6. the d8?d15 schottky type diode br idge bypass is recommended only for higher power levels (class 3 operati on). for lower power levels, such as class 1 and class 2, the diodes can be removed. when the si3402b is used in external diode bridge configuration, it requires that at least one pair of the ctx and spx pins be connected to the poe voltage in put terminals (to the input of the external bridge).
si3402b-evb 2 rev. 1.1 optional bypass diodes for >7w applications are in parallel with c10-c17 vpos is a emi and esd plane. use top layer. vneg is a thermal plane as wel as esd and emi. use thermal vias to at least 1 inch square plane on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter. connect inductor and output filter caps together minimizing area of return loop and then connect to output ground plane. ni = not installed 5v at least one pair of ct1/ct2 or sp1/sp2 should be connected. swo vpos vneg fb vss vneg d13 ss2150 l5 330 ohm c20 ni u1 si3402b erout 1 nc 2 vdd 3 nc 4 nploss 5 rdet 6 hso 7 rcl 8 vneg 9 sp2 10 sp1 11 vpos 12 ct2 13 ct1 14 vssa 15 nc 16 nc 17 swo 18 vss2 19 fb 20 d12 ss2150 d9 ss2150 l2 330 ohm r7 47k j11 bnd_post c1 1uf c13 1nf fb1 30 ohm c17 1nf c12 1nf l3 330 ohm c16 1nf + c5 560uf c11 1nf c15 1nf c10 1nf c14 1nf d14 ss2150 j12 bnd_post j1 rj-45 mx0+ 1 mx0- 3 mx1+ 4 pwr2 8 pwr3 9 pwr4 10 ct 2 led_k2 k2 led_a2 a2 led_k1 k1 led_a1 a1 pwr1 7 ct/mx1- 5 mx1- 6 pwr5 11 tp2 ni r3 48.7 l4 330 ohm + c2 12uf c8 0.1uf d8 ss2150 d10 ss2150 d15 ss2150 c4 1uf l1 33uh r9 100 c3 1uf c18 0.1uf r1 330 r2 49.9k c7 1nf tp6 ni c6 22uf d11 ss2150 c19 ni tp5 ni tp4 ni r6 8.66k tp3 ni r4 24.3k r5 3.24k d1 pds5100 figure 1. si3402b schematic?5 v, class 3 pd
si3402b-evb rev. 1.1 3 figure 2. top silkscreen
si3402b-evb 4 rev. 1.1 figure 3. top layer
si3402b-evb rev. 1.1 5 figure 4. internal 1 (layer 2)
si3402b-evb 6 rev. 1.1 figure 5. internal 2 (layer 3)
si3402b-evb rev. 1.1 7 figure 6. bottom layer
si3402b-evb 8 rev. 1.1 3. bill of materials the table below is the bom listing for the standard 5 v evaluation board with a popular option for class 3. for class 1 and class 2 designs, in addition to updating the classification resistor (r3), the external diode bridge (d8?d15) can be removed to reduce bom costs. table 1. si3402b-evb bill of materials ni qty value ref rating v tol type pcb footprint mfr part number mfr 3 1 f c1, c3, c4 100 v 10% x7r c1210 c1210x7r101-105k venkel 1 12 f c2 100 v 20% alum_elec c2.5x6.3mm-rad eeufc2a120 panasonic 1 560 f c5 6.3 v 20% alum_elec c3.5x8mm-rad eeufm0j561 panasonic 1 22 f c6 6.3 v 20% x5r c0805 c0805x5r6r3-226m venkel 1 1 nf c7 50 v 1% c0g c0805 c0805c0g500-102f venkel 1 0.1 f c8 16 v 10% x7r c0805 c0805x7r160-104k venkel 8* 1 nf c10, c11, c12, c13, c14, c15, c16, c17 100 v 10% x7r c0603 c0603x7r101-102k venkel 1 0.1 f c18 100 v 10% x7r c0805 c0805x7r101-104k venkel ni 1 150 pf c19 16 v 10% x7r c0805 c0805x7r160-151k venkel ni 1 3.3 nf c20 16 v 10% x7r c0805 c0805x7r160-332k venkel 1 pds5100 d1 5 a 100 v schottky powerdi-5 pds5100h-13 diodes inc. 8 ss2150 d8, d9, d10, d11, d12, d13, d14, d15 2 a 150 v single do-214ac ss2150-ltp mcc 130 ? fb1 3000 ma smt l0805 BLM21PG300SN1 murata 1 rj-45 j1 receptacle rj45-si-52004 si-52003-f bel 2 bnd_post j11, j12 15 a banana banana jack 101 abbatron hh smith 1 33 h l1 5.2 a 20% shielded ind-spd mss1278-333ml coilcraft 4 330 ? l2, l3, l4, l5 1500 ma smt l0805 blm21pg331sn1 murata 1 330 ? r1 1/10 w 1% thickfilm r0805 cr0805-10w-3300f venkel 149.9k ? r2 1/8 w 1% thickfilm r0805 cr0805-8w-4992f venkel 1 48.7 ? r3 1/8 w 1% thickfilm r0805 crcw080548r7fkta vishay 124.3k ? r4 1/8 w 1% thickfilm r0805 crcw080524k3fkea vishay 13.24k ? r5 1/8 w 1% thickfilm r0805 crcw08053k24fkea vishay 18.66k ? r6 1/10 w 1% thickfilm r0805 cr080510w-8661f venkel 147k ? r7 1/10 w 5% thickfilm r0805 cr0805-10w-473j venkel 1 100 ? r9 1/2 w 1% thickfilm r1210 cr1210-2w-1000f venkel ni 5 black tp2, tp3, tp4, tp5, tp6 loop testpoint 5001 keystone 1 si3402b u1 100 v pd qfn20n5x5p0.8 si3402b silabs *note: c10?c17 are populated by default. see the ?surge? section in an956 for more information.
si3402b-evb rev. 1.1 9 4. bom options the si3402b non-isolat ed evb has been compensated for eight different output voltage and filter combinations: ? 3.3 v output standard esr 1000 f 6.3 v filter ? 5 v output standard esr 1000 f 6.3 v filter ? 9 output standard esr 470 f 16 v filter ? 12 v output standard esr 470 f 16 v filter ? 3.3 v output low esr 560 f 6.3 v filter ? 5 v output low esr 560 f 6.3 v filter ? 9 v output low esr 330 f 16 v filter ? 12 v output low esr 330 f 16 v filter for the standard esr capacito r, the esr increase at very low temperatures may caus e a loop stability issue. a typical evaluation board has been shown to exhibit instability under ve ry heavy loads at ?20 c. due to self-heating, this condition is not a great concern. howeve r, using a low esr filter ca pacitor solves this problem (but requires some recompensation of the feedback loop ). the low esr capacitor also improves load transient response and output ripple. the si3402b (non?isolated) evb was designed with a very simple co mpensation consisti ng of r7 and c7. the standard evaluation board is optimized for a standard esr filter capacitor for 5 v output. the following table gives the options that have been tested for other situations. v out r6 (to adjust output voltage) filter cap c5 (type fm are low esr) filter cap part number (panasonic) r7 c7 3.3 v 4.64 k : 1000f, 6.3v eca0jm102 47k : 1nf 3.3 v 4.64 k : 560 f, 6.3 v eeufm0j561 47 k : 1nf 5.0 v 8.66 k : 1000f, 6.3v eca0jm102 47k : 1nf 5.0 v 8.66 k : 560 f, 6.3 v eeufm0j561 47 k : 1nf 9.0 v 18.2 k : 470 f, 16 v eca1cm471 47 k : 1nf 9.0 v 18.2 k : 330 f, 16 v eeufm1c331 47 k : 1nf 12.0 v 25.5 k : 470 f, 16 v eca1cm471 47 k : 1nf 12.0 v 25.5 k : 330 f, 16 v eeufm1c331 47 k : 1nf
si3402b-evb 10 rev. 1.1 a ppendix ?si3402b d esign and l ayout c hecklist introduction although the evb design is pr e-configured as a class 3 pd with 5 v ou tput, the schematics and layouts can easily be adapted to meet a wide variety of common output voltages and power levels. the complete evb design databases for the stan dard 5 v/class 3 config uration are located at www.silabs.com/poe under the ?documentation? link. silicon labs strongly reco mmends using these evb schematics and layout files as a starting point to ens ure robust performance and avoid common mistakes in the schematic capture and pcb layout processes. following are recommended design checklists that can assist in trouble-free development of robust pd designs. refer also to the si3402b data sheet and an956 when using the following checklists. 1. design planning checklist: a. determine if your design requires an isolated or non-isolated topology. for more information, see section 4 of an956. b. silicon labs strongly recommends using the evb schem atics and layout files as a starting point as you begin integrating the si3402b into your system design process. c. determine your load?s power requirements (i.e., v out and i out consumed by the pd, including the typical expected transient surge conditions). in ge neral, to achieve the highest overall efficiency performance of the si3402b, choose the highest voltage used in your pd and then post regulate to the lower supply rails, if necessary. d. if your pd design consumes > 7 w, be sure to bypass the si3402b?s on-chip diode bridges with external schottky diode bridges or discrete diodes. bypassi ng the si3402b?s on-chip di ode bridges with external bridges or discrete schottky diodes is required to help spread the heat generated in designs dissipating > 7w. e. based on your required pd power level, select the appropriate class resistor value by referring to table 3 of an956. this sets the rclass resistor (r3 in figure 1 on page 2). 2. general design checklist items: a. esd caps (c10?c17 in figure 1) are strongly recommended for designs where system-level esd (iec6100-4-2) must provide >15 kv tolerance. b. if your design uses an aux supply, be sure to include a 3 w surge limiting resistor in series with the aux supply for hot insertion. refer to an956 when aux supply is 48 v. c. silicon labs strongly recommen ds the inclusion of a minimum load (250 mw) to avoid switcher pulsing when no load is present and to avoid false disconnection when less th an 10 ma is drawn from the pse. if your load is not at least 250 mw, add a resistor load to dissipate at least 250 mw. d. if using ploss function, make sure it?s properly te rminated for connection in your pd subsystem. if ploss is not needed, leave this pin floating. 3. layout guidelines: a. make sure vneg pin of the si3402b is connected to the backside of the qfn package with an adequate thermal plane, as noted in the data sheet and an956. b. keep the trace length from connecting to swo and re tuning to vss2 as short as possible. make all of the power (high current) traces as short, direct, and thick as possible. it is a good practice on a standard pcb board to make the traces an absolute minimum of 15 mils (0.381 mm) per ampere. c. usually, one standard via handles 200 ma of current. if the trace needs to conduct a significant amount of current from one plane to the other, use multiple vias.
si3402b-evb rev. 1.1 11 d. keep the circular area of the loop from the swit cher fet output to the in ductor or transformer and returning from th e input filter capacitors (c1?c4 ) to vss2 as small a diameter as possible. also, minimize the circular area of the loop from the output of the inductor or transformer to the schottky diode and returning through the first st age output filter capacitor back to the inductor or transformer as small as possible. if possible, keep the direction of current flow in these two loops the same. e. keep the high power traces as short as possible. f. keep the feedback and loop st ability components as far from the transformer/inductor and noisy power traces as possible. g. if the outputs have a ground plane or positive out put plane, do not connect the high current carrying components and the filter capacitors through the plane. connect them together, and then connect to the plane at a single point. h. as a convenience in layout, please note that the ic is symmetrical with respect to ct1, ct2, sp1, and sp2. these leads can be interchanged. at least one pair of ct1/ct2 or sp1/sp2 should be connected. to help ensure first-pass success, submit your schematics and layout files to poeinfo@silabs.com for review. other technical questions may be sent to this e-mail address as well.
si3402b-evb 12 rev. 1.1 d ocument c hange l ist revision 1.0 to revision 1.1 ? initial release of si3 402b-evb user?s guide, modified from si3402-evb user?s guide revision 1.0.
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